The present invention disclosed herein relates to a semiconductor substrate manufacturing apparatus and a substrate treating method, and more particularly, to an apparatus and method for performing a reflow treating process on a semiconductor wafer and this application being co-filed with sister application Semigear-30A, both of these applications each being a division of application Ser. No. 13/987,512, filed on Aug. 1, 2013, now U.S. Pat. No. 9,226,407, issued on 29 Dec. 2015 which was originally a co-filed application of Semigear-28 (application Ser. No. 13/987,511, Apparatus and Method for Treating a Substrate, Publication Number US-2015-0034702-A1), and Semigear-32 (application Ser. No. 13/987,510, Reflow Treating Unit and Substrate Treating Apparatus, Publication Number US-2015-0034699-A1) which were filed simultaneously herewith, which were each a CIP application of U.S. application Ser. No. 13/573,486, filed Sep. 17, 2012 (Semigear-24), which is a CIP of application Ser. No. 12/930,462, now U.S. Pat. No. 8,274,161, which is a CIP of application Ser. No. 12/930,203, now U.S. Pat. No. 8,252,678, which is a CIP of application Ser. No. 12/653,454, now U.S. Pat. No. 7,982,320, which is a DIV of application Ser. No. 11/482,838, now U.S. Pat. No. 7,632,750, which is a CIP of application Ser. No. 10/832,782, now U.S. Pat. No. 7,008,879, which is a DIV of application Ser. No. 10/186,823, now U.S. Pat. No. 6,827,789, each of the above being incorporated herein by reference in their entirety.
With the high integration of a semiconductor device, the number of connection pads for connecting a semiconductor chip on which a semiconductor integrated circuit is formed to an external circuit increases. Thus, the number of lead lines of a semiconductor package that is mounted on a printed circuit board (PCB) significantly increases.
As the number of the lead lines increases, packaging technologies to which a lead frame is applied according to a related art are difficult to be applied to a highly-integrated semiconductor chip including about 500 pins or more.
Thus, ball grid array (BGA) package technologies as new concepts in which output terminals of a semiconductor package are disposed by using a wide lower surface of the semiconductor package are being developed.
In the BGA package technologies, a semiconductor chip is mounted on a PCB, and a solder ball is disposed to correspond to an output terminal of the PCB. Also, an integrated circuit of a semiconductor package is electrically connected to an external circuit of an electrical device through the output terminal of the PCB and the solder ball connected to the output terminal.
Here, the solder ball is disposed on a surface opposite to the PCB on which the semiconductor integrated circuit is mounted. Also, a soldering process for electrically connecting the solder ball to the output terminal of the PCB is required.
Here, an apparatus for soldering the semiconductor chip to a surface of the PCB at a predetermined temperature to cure the soldered portion after the semiconductor chip is mounted on the surface of the PCB may be called a reflow apparatus.
In the reflow apparatus, the PCB on which the solder ball is placed is put in a heating furnace to heat the solder ball for a predetermined time at a predetermined temperature. As a result, the solder ball may be soldered to the output terminal of the PCB.
Generally, in a substrate treating apparatus for performing a reflow treating process, a portion of equipment constituting an exhaust device exhausting a fluid within a reflow treating unit may be frequently replaced due to fluxes and impurities which are generated during the reflow process.